PIC16F688-I/ML
Case: | QFN-16S(4x4-0.65) |
Number of I/O: | 12 |
RAM memory: | 256B |
FLASH memory: | 7kB |
Supply voltage range: | 2V~5,5V |
Frequency: | 20,000MHz |
EEPROM memory: | 256B |
Case: | QFN-16S(4x4-0.65) |
Number of I/O: | 12 |
RAM memory: | 256B |
FLASH memory: | 7kB |
Supply voltage range: | 2V~5,5V |
Frequency: | 20,000MHz |
EEPROM memory: | 256B |
Architecture: | 8-bit |
Operating temperature (range): | -40°C ~ 85°C |
ADC: | YES |
CAN interface: | NO |
DAC: | NO |
ETHERNET interface: | NO |
Encryption: | NO |
SPI interface: | NO |
TWI (I2C) interface: | NO |
UART/USART interface: | YES |
USB interface: | NO |
Manufacturer: | MICROCHIP |
FEATURES:
- Efficient RISC architecture; 35 instructions executed in one clock cycle (except for jumps); 1 cycle = 200ns for fCLK = 20MHz
- 8-level hardware stack (13 bits)
- Internal oscillator: 8MHz or 31kHz
- Power-On Reset function
- Brown-Out Reset function
- Power-Up Timer to extend the reset signal for 64ms after power-on
- Oscillator Start-Up Timer to extend the reset signal until the oscillator frequency stabilizes
- Programmable Watchdog with built-in internal oscillator
- Programmable code protection from read-out
- Maximum clock frequency: 20MHz
- Operating temperature: -40°C to 85°C
PROGRAM MEMORY:
- Memory type: FLASH
- Capacity: 7kB
- Memory word length: 14-bit
- In-System Programming capability via 2 pins - ICSP™
DATA MEMORY:
- 256B SRAM
- 256B EEPROM
PERIPHERALS:
- 8-channel 10-bit A/D converter
- 12 I/O pins capable of directly driving LEDs
- 8-bit Timer with prescaler Timer0
- Advanced 16-bit Timer with prescaler Timer1
- 2x Comparator with programmable voltage reference
- Advanced asynchronous/synchronous serial communication module EUSART
ELECTRICAL PARAMETERS:
- Supply voltage: 2V to 5.5V
- Current consumption:
Active mode: 220mA for fCLK = 4MHz, VDD = 2.0V
Sleep mode: 50nA for VDD=2.0V
Microchip’s 8-bit PIC microcontrollers with RISC architecture are characterized by high power efficiency at the I/O pins, low current consumption, and an integrated Watchdog and Power-On Reset function. With two separate internal buses—address and data—they use pipelined processing. All registers, including I/O ports, timers, and instruction counters, can have their contents modified in one operation. All instructions take one cycle (200ns at 20MHz), except for jump instructions, which take 2 cycles. Available in 6-, 8-, 14-, 18-, 20-, 28-, 40-, 44-, 64-, 80-, and 100-pin packages with FLASH or OTP program memory, non-volatile EEPROM data memory, and operational RAM. Designed for a wide range of applications, from simple projects to complex "high-performance" systems. In-System Programming (ISP) enables most devices to be programmed directly in the system.